Raymond Toy pushed to branch issue-355-solaris-x86-fp-trap-handler at cmucl / cmucl

Commits:

• 82c50cbc
  by Raymond Toy at 2024-09-07T06:41:04-07:00

  Tighten up float-modes deftype
  
  The existing `float-modes` type is `(unsigned-byte 24)`.  However, for
  x87, the float mode can be at least 26 bits long.  This showed up
  running the unit test suite.  Examining the bits in the control word
  shows that 26 is the max, if you ignore the reserved bits at the high
  part of the control word.
  
  For sse2, the mxcsr register only has 16 defined bits.
  
  Thus, split `float-modes` into separate types, one for x87 and one for sse2.
  

1 changed file:

• src/compiler/x86/float-sse2.lisp

Changes:

 ;;;; Float mode hackery:

-(deftype float-modes () '(unsigned-byte 24))

+(deftype x87-float-modes () '(unsigned-byte 32))

+(deftype sse2-float-modes () '(unsigned-byte 16))

 ;; For the record, here is the format of the MXCSR register.

 ;;

 ;;  0         invalid operation flag

 ;;

 ;; See below for rounding control

-(defknown sse2-floating-point-modes () float-modes (flushable))

-(defknown ((setf sse2-floating-point-modes)) (float-modes) float-modes)

+(defknown sse2-floating-point-modes () sse2-float-modes (flushable))

+(defknown ((setf sse2-floating-point-modes)) (sse2-float-modes) sse2-float-modes)

 ;; Returns exactly the mxcsr register, except the masks are flipped

 ;; because we want exception enable flags, not masks.

 ;; 10   double precision (53 bits)

 ;; 11   double extended precision (64 bits)

-(defknown x87-floating-point-modes () float-modes (flushable))

-(defknown ((setf x87-floating-point-modes)) (float-modes)

-  float-modes)

+(defknown x87-floating-point-modes () x87-float-modes (flushable))

+(defknown ((setf x87-floating-point-modes)) (x87-float-modes)

+  x87-float-modes)

 ;; Extract the control and status words from the FPU.  The low 16 bits

 ;; contain the status word, and the high 16 bits contain the control.