| ... |
... |
@@ -647,7 +647,7 @@ os_sigcontext_x87_modes(ucontext_t *scp) |
|
647
|
647
|
cw = fpr->fp_reg_set.fpchip_state.state[0] & 0xffff;
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|
648
|
648
|
sw = fpr->fp_reg_set.fpchip_state.state[1] & 0xffff;
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|
649
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649
|
|
|
650
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|
- DPRINTF(1, (stderr, "os_sigcontext_x87 cw, sw = #x%04x #x%04x\n", cw, sw));
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650
|
+ DPRINTF(0, (stderr, "os_sigcontext_x87 cw, sw = #x%04x #x%04x\n", cw, sw));
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651
|
651
|
|
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652
|
652
|
return (cw << 16) | sw;
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653
|
653
|
}
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| ... |
... |
@@ -661,12 +661,12 @@ os_set_sigcontext_x87_modes(ucontext_t *scp, unsigned int modes) |
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661
|
661
|
|
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662
|
662
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sw = modes & 0xffff;
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663
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663
|
cw = (modes >> 16) & 0xffff;
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|
664
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|
-
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|
|
664
|
+
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665
|
665
|
fpr->fp_reg_set.fpchip_state.state[0] = cw;
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|
666
|
666
|
fpr->fp_reg_set.fpchip_state.state[1] = sw;
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667
|
667
|
|
|
668
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|
- DPRINTF(1, (stderr, "os_set_sigcontext_x87 modes = #x%08x\n", modes));
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|
669
|
|
- DPRINTF(1, (stderr, "os_set_sigcontext_x87 cw, sw = #x%04x #x%04x\n", cw, sw));
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668
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+ DPRINTF(0, (stderr, "os_set_sigcontext_x87 modes = #x%08x\n", modes));
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|
|
669
|
+ DPRINTF(0, (stderr, "os_set_sigcontext_x87 cw, sw = #x%04x #x%04x\n", cw, sw));
|
|
670
|
670
|
}
|
|
671
|
671
|
|
|
672
|
672
|
|
| ... |
... |
@@ -679,7 +679,7 @@ os_sigcontext_sse2_modes(ucontext_t *scp) |
|
679
|
679
|
|
|
680
|
680
|
fpr = &scp->uc_mcontext.fpregs;
|
|
681
|
681
|
mxcsr = fpr->fp_reg_set.fpchip_state.mxcsr;
|
|
682
|
|
- DPRINTF(1, (stderr, "os_sigcontext_sse2 mxcsr = #x%08lx\n", mxcsr));
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|
|
682
|
+ DPRINTF(0, (stderr, "os_sigcontext_sse2 mxcsr = #x%08lx\n", mxcsr));
|
|
683
|
683
|
|
|
684
|
684
|
return mxcsr;
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|
685
|
685
|
}
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| ... |
... |
@@ -692,7 +692,7 @@ os_set_sigcontext_sse2_modes(ucontext_t *scp, unsigned int modes) |
|
692
|
692
|
|
|
693
|
693
|
fpr->fp_reg_set.fpchip_state.mxcsr = modes;
|
|
694
|
694
|
|
|
695
|
|
- DPRINTF(1, (stderr, "os_set_sigcontext_sse2 mxcsr = #x%08x\n", modes));
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|
|
695
|
+ DPRINTF(0, (stderr, "os_set_sigcontext_sse2 mxcsr = #x%08x\n", modes));
|
|
696
|
696
|
}
|
|
697
|
697
|
#endif
|
|
698
|
698
|
|
| ... |
... |
@@ -702,19 +702,19 @@ os_set_sigcontext_fpu_modes(ucontext_t *scp, uint32_t modes) |
|
702
|
702
|
unsigned short cw, sw;
|
|
703
|
703
|
fpregset_t *fpr;
|
|
704
|
704
|
unsigned int state;
|
|
705
|
|
-
|
|
|
705
|
+
|
|
706
|
706
|
fpr = &scp->uc_mcontext.fpregs;
|
|
707
|
707
|
|
|
708
|
708
|
cw = modes & 0x3f;
|
|
709
|
709
|
sw = (modes >> 7) &0x3f;
|
|
710
|
710
|
|
|
711
|
|
- DPRINTF(1, (stderr, "modes = 0x%08x\n", modes));
|
|
712
|
|
- DPRINTF(1, (stderr, "cw = 0x%04x\n", cw));
|
|
713
|
|
- DPRINTF(1, (stderr, "sw = 0x%04x\n", sw));
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|
|
711
|
+ DPRINTF(0, (stderr, "modes = 0x%08x\n", modes));
|
|
|
712
|
+ DPRINTF(0, (stderr, "cw = 0x%04x\n", cw));
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|
|
713
|
+ DPRINTF(0, (stderr, "sw = 0x%04x\n", sw));
|
|
714
|
714
|
|
|
715
|
715
|
fpr->fp_reg_set.fpchip_state.state[0] = cw;
|
|
716
|
716
|
fpr->fp_reg_set.fpchip_state.state[1] = sw;
|
|
717
|
|
-
|
|
|
717
|
+
|
|
718
|
718
|
#ifdef FEATURE_SSE2
|
|
719
|
719
|
/*
|
|
720
|
720
|
* Add in the SSE2 part, if we're running the sse2 core.
|
| ... |
... |
@@ -722,7 +722,7 @@ os_set_sigcontext_fpu_modes(ucontext_t *scp, uint32_t modes) |
|
722
|
722
|
if (fpu_mode == SSE2) {
|
|
723
|
723
|
unsigned long mxcsr = modes & 0xffff;
|
|
724
|
724
|
|
|
725
|
|
- DPRINTF(1, (stderr, "SSE2 modes = %08lx\n", mxcsr));
|
|
|
725
|
+ DPRINTF(0, (stderr, "SSE2 modes = %08lx\n", mxcsr));
|
|
726
|
726
|
fpr->fp_reg_set.fpchip_state.mxcsr = mxcsr;
|
|
727
|
727
|
|
|
728
|
728
|
modes |= mxcsr;
|