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at 2021-01-11T05:37:39+00:00

Fix #95: Fix disassembly for je and movzx/movsx instructions

We were printing `jeq` for the branch on equal instruction, but it
should be `je`.  This is fixed by changing the order of the options in
the `defconstant` `conditions`.  The first in the list is the
preferred value, so we can write `je`, `jeq`, or `jz`, but these will
all get printed out as `je` instead of the previous `jeq`.

For `movzx` and `movsx`, we need to specify the size of the memory object
to match Intel syntax.  This is done by changing the size of the
`ext-reg-reg/mem` format so that the reg/mem field has type
`sized-reg/mem` instead of just `reg/mem`.

Finally, we just added a note that the `break` instruction is really
the `int3` instruction.  I don't know why it's called `break` instead
of `int3`.

@@ -10,3 +10,8 @@
  ;; x86: cross-x86-x86
  ;; sparc: cross-sparc-sparc
 +;; This is also used to easily change the order of x86::conditions
 +;; constant so that we prefer je instead of jeq.  Without a
 +;; cross-compile we'd need to handle the refefintion of the
 +;; defconstant in a different way.  See issue #95.
++

@@ -255,12 +255,15 @@
         (= (tn-offset thing) 0)))
  (eval-when (compile load eval)
 +;; If a line has more than one value, then these are all synonyms, but
 +;; the first one is the one that is preferred when printing the
 +;; condition code out.
  (defconstant conditions
    '((:o . 0)
      (:no . 1)
      (:b . 2) (:nae . 2) (:c . 2)
      (:nb . 3) (:ae . 3) (:nc . 3)
 -    (:eq . 4) (:e . 4) (:z . 4)
 +    (:e . 4) (:eq . 4) (:z . 4)
      (:ne . 5) (:nz . 5)
      (:be . 6) (:na . 6)
      (:nbe . 7) (:a . 7)
@@ -794,7 +797,7 @@
    (op      :field (byte 7 1))
    (width   :field (byte 1 0)	:type 'width)
    (reg/mem :fields (list (byte 2 14) (byte 3 8))
 -	   			:type 'reg/mem)
 +	   			:type 'sized-reg/mem)
    (reg     :field (byte 3 11)	:type 'reg)
    ;; optional fields
    (imm))
@@ -832,7 +835,10 @@
  (disassem:define-instruction-format
      (accum-reg/mem 16
       :include 'reg/mem :default-printer '(:name :tab accum ", " reg/mem))
 -  (reg/mem :type 'reg/mem)		; don't need a size
 +  ;; This format uses the accumulator, so the size is known; therefore
 +  ;; we don't really need to print out the memory size, but let's do
 +  ;; it for consistency.
 +  (reg/mem :type 'sized-reg/mem)
    (accum :type 'accum))
  ;;; Same as reg-reg/mem, but with a prefix of #b00001111
@@ -843,7 +849,7 @@
    (op      :field (byte 7 9))
    (width   :field (byte 1 8)	:type 'width)
    (reg/mem :fields (list (byte 2 22) (byte 3 16))
 -	   			:type 'reg/mem)
 +	   			:type 'sized-reg/mem)
    (reg     :field (byte 3 19)	:type 'reg)
    ;; optional fields
    (imm))
@@ -865,7 +871,7 @@
    (prefix  :field (byte 8 0)  :value #b00001111)
    (op      :field (byte 8 8))
    (reg/mem :fields (list (byte 2 22) (byte 3 16))
 -	                      :type 'reg/mem)
 +	                      :type 'sized-reg/mem)
    (reg     :field (byte 3 19) :type 'reg)
    ;; optional fields
    (imm))
@@ -1129,7 +1135,8 @@
  	      (error "Bogus args to XCHG: ~S ~S" operand1 operand2)))))))
  (define-instruction lea (segment dst src)
 -  (:printer reg-reg/mem ((op #b1000110) (width 1)))
 +  ;; Don't need to print out the width for the LEA instruction
 +  (:printer reg-reg/mem ((op #b1000110) (width 1) (reg/mem nil :type 'reg/mem)))
    (:emitter
     (assert (dword-reg-p dst))
     (emit-byte segment #b10001101)
@@ -2112,6 +2119,7 @@
         (nt "Function end breakpoint trap"))
      )))
 +;; This is really the int3 instruction.
  (define-instruction break (segment code)
    (:declare (type (unsigned-byte 8) code))
    (:printer byte-imm ((op #b11001100)) '(:name :tab code)

Raymond Toy pushed to branch master at cmucl / cmucl

Commits:

2 changed files:

Changes: