Raymond Toy pushed to branch issue-355-solaris-x86-fp-trap-handler at cmucl / cmucl
Commits:
-
959faae1
by Raymond Toy at 2024-08-29T20:47:11-07:00
3 changed files:
Changes:
| ... | ... | @@ -482,6 +482,13 @@ |
| 482 | 482 | (let* ((modes (sigcontext-floating-point-modes
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| 483 | 483 | (alien:sap-alien scp (* unix:sigcontext)))))
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| 484 | 484 | (format t "Current modes: ~32,'0b~%" modes)
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| 485 | + (format t "sigcontext x87: ~32,'0b~%"
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| 486 | + (sigcontext-floating-point-modes-x87
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| 487 | + (alien:sap-alien scp (* unix:sigcontext))))
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| 488 | + (format t "sigcontext sse2: ~32,'0b~%"
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| 489 | + (sigcontext-floating-point-modes-sse2
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| 490 | + (alien:sap-alien scp (* unix:sigcontext))))
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| 491 | + |
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| 485 | 492 | (multiple-value-bind (fop operands)
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| 486 | 493 | (let ((sym (find-symbol "GET-FP-OPERANDS" "VM")))
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| 487 | 494 | (if (fboundp sym)
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| ... | ... | @@ -529,14 +536,19 @@ |
| 529 | 536 | (format t "new x87 modes: ~32,'0b~%" (vm::x87-floating-point-modes))
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| 530 | 537 | (format t "new sse2 modes: ~32,'0b~%" (vm::sse2-floating-point-modes)))
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| 531 | 538 | (let* ((trap-bit (third (assoc code +fpe-code-info-alist+)))
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| 532 | - (new-modes
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| 533 | - (dpb (logandc2 (ldb float-exceptions-byte modes)
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| 534 | - trap-bit)
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| 535 | - float-exceptions-byte modes)))
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| 536 | - (format t "New modes: ~32,'0b~%" new-modes)
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| 537 | - (setf (sigcontext-floating-point-modes)
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| 538 | - (alien:sap-alien scp (* unix:sigcontext))
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| 539 | - new-modes))))))
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| 539 | + (x87-modes (sigcontext-floating-point-modes-x87
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| 540 | + (alien:sap-alien scp (* unix:sigcontext))))
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| 541 | + (sse2-modes (sigcontext-floating-point-modes-sse2
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| 542 | + (alien:sap-alien scp (* unix:sigcontext)))))
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| 543 | + (format t "Trap bit: ~D~%" trap-bit)
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| 544 | + (format t "New sigcontext x87: ~32,'0b~%" (logandc2 x87-modes trap-bit))
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| 545 | + (format t "New sigcontext sse2: ~32,'0b~%" (logandc2 sse2-modes trap-bit))
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| 546 | + (%set-sigcontext-floating-point-modes-x87
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| 547 | + (alien:sap-alien scp (* unix:sigcontext))
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| 548 | + (logandc2 x87-modes trap-bit))
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| 549 | + (%set-sigcontext-floating-point-modes-sse2
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| 550 | + (alien:sap-alien scp (* unix:sigcontext))
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| 551 | + (logandc2 sse2-modes trap-bit)))))))
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| 540 | 552 | |
| 541 | 553 | (macrolet
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| 542 | 554 | ((with-float-traps (name merge-traps docstring)
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| ... | ... | @@ -378,6 +378,41 @@ |
| 378 | 378 | |
| 379 | 379 | (defsetf sigcontext-floating-point-modes %set-sigcontext-floating-point-modes)
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| 380 | 380 | |
| 381 | +#+solaris
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| 382 | +(progn
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| 383 | +(defun sigcontext-floating-point-modes-x87 (scp)
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| 384 | + (declare (type (alien (* unix:sigcontext)) scp))
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| 385 | + (let ((fn (extern-alien "os_sigcontext_x87_modes"
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| 386 | + (function (integer 32)
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| 387 | + (* unix:sigcontext)))))
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| 388 | + (alien-funcall fn scp)))
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| 389 | + |
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| 390 | +(defun %set-sigcontext-floating-point-modes-x87 (scp new-modes)
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| 391 | + (declare (type (alien (* unix:sigcontext)) scp))
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| 392 | + (let ((fn (extern-alien "os_set_sigcontext_x87_modes"
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| 393 | + (function c-call:void
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| 394 | + (* unix:sigcontext)
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| 395 | + c-call:unsigned-int))))
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| 396 | + (alien-funcall fn scp new-modes)
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| 397 | + new-modes))
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| 398 | +
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| 399 | +(defun sigcontext-floating-point-modes-sse2 (scp)
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| 400 | + (declare (type (alien (* unix:sigcontext)) scp))
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| 401 | + (let ((fn (extern-alien "os_sigcontext_sse2_modes"
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| 402 | + (function (integer 32)
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| 403 | + (* unix:sigcontext)))))
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| 404 | + (alien-funcall fn scp)))
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| 405 | + |
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| 406 | +(defun %set-sigcontext-floating-point-modes-sse2 (scp new-modes)
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| 407 | + (declare (type (alien (* unix:sigcontext)) scp))
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| 408 | + (let ((fn (extern-alien "os_set_sigcontext_sse2_modes"
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| 409 | + (function c-call:void
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| 410 | + (* unix:sigcontext)
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| 411 | + c-call:unsigned-int))))
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| 412 | + (alien-funcall fn scp new-modes)
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| 413 | + new-modes))
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| 414 | +)
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| 415 | + |
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| 381 | 416 | |
| 382 | 417 | ;;; EXTERN-ALIEN-NAME -- interface.
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| 383 | 418 | ;;;
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| ... | ... | @@ -615,9 +615,9 @@ os_sigcontext_fpu_modes(ucontext_t *scp) |
| 615 | 615 | |
| 616 | 616 | modes = ((cw & 0x3f) << 7) | (sw & 0x3f);
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| 617 | 617 | |
| 618 | - DPRINTF(0, (stderr, "cw = 0x%04x\n", cw));
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| 619 | - DPRINTF(0, (stderr, "sw = 0x%04x\n", sw));
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| 620 | - DPRINTF(0, (stderr, "modes = 0x%08x\n", modes));
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| 618 | + DPRINTF(0, (stderr, "os_sigcontext_fpu cw = 0x%04x\n", cw));
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| 619 | + DPRINTF(0, (stderr, "os_sigcontext_fpu sw = 0x%04x\n", sw));
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| 620 | + DPRINTF(0, (stderr, "os_sigcontext_fpu modes = 0x%08x\n", modes));
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| 621 | 621 |
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| 622 | 622 | #ifdef FEATURE_SSE2
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| 623 | 623 | /*
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| ... | ... | @@ -627,7 +627,7 @@ os_sigcontext_fpu_modes(ucontext_t *scp) |
| 627 | 627 | unsigned long mxcsr;
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| 628 | 628 | |
| 629 | 629 | mxcsr = fpr->fp_reg_set.fpchip_state.mxcsr;
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| 630 | - DPRINTF(0, (stderr, "SSE2 modes = %08lx\n", mxcsr));
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| 630 | + DPRINTF(0, (stderr, "os_sigcontext_fpu SSE2 modes = %08lx\n", mxcsr));
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| 631 | 631 | |
| 632 | 632 | modes |= mxcsr;
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| 633 | 633 | }
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| ... | ... | @@ -637,6 +637,65 @@ os_sigcontext_fpu_modes(ucontext_t *scp) |
| 637 | 637 | return modes;
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| 638 | 638 | }
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| 639 | 639 | |
| 640 | +unsigned int
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| 641 | +os_sigcontext_x87_modes(ucontext_t *scp)
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| 642 | +{
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| 643 | + unsigned short cw, sw;
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| 644 | + fpregset_t *fpr;
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| 645 | + fpr = &scp->uc_mcontext.fpregs;
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| 646 | + |
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| 647 | + cw = fpr->fp_reg_set.fpchip_state.state[0] & 0xffff;
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| 648 | + sw = fpr->fp_reg_set.fpchip_state.state[1] & 0xffff;
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| 649 | + |
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| 650 | + DPRINTF(1, (stderr, "os_sigcontext_x87 cw, sw = #x%04x #x%04x\n", cw, sw));
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| 651 | + |
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| 652 | + return (cw << 16) | sw;
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| 653 | +}
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| 654 | + |
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| 655 | +void
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| 656 | +os_set_sigcontext_x87_modes(ucontext_t *scp, unsigned int modes)
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| 657 | +{
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| 658 | + unsigned short cw, sw;
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| 659 | + fpregset_t *fpr;
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| 660 | + fpr = &scp->uc_mcontext.fpregs;
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| 661 | + |
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| 662 | + sw = modes & 0xffff;
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| 663 | + cw = (modes >> 16) & 0xffff;
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| 664 | +
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| 665 | + fpr->fp_reg_set.fpchip_state.state[0] = cw;
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| 666 | + fpr->fp_reg_set.fpchip_state.state[1] = sw;
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| 667 | + |
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| 668 | + DPRINTF(1, (stderr, "os_set_sigcontext_x87 modes = #x%08x\n", modes));
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| 669 | + DPRINTF(1, (stderr, "os_set_sigcontext_x87 cw, sw = #x%04x #x%04x\n", cw, sw));
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| 670 | +}
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| 671 | + |
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| 672 | + |
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| 673 | +#ifdef FEATURE_SSE2
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| 674 | +unsigned int
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| 675 | +os_sigcontext_sse2_modes(ucontext_t *scp)
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| 676 | +{
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| 677 | + unsigned long mxcsr;
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| 678 | + fpregset_t *fpr;
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| 679 | + |
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| 680 | + fpr = &scp->uc_mcontext.fpregs;
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| 681 | + mxcsr = fpr->fp_reg_set.fpchip_state.mxcsr;
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| 682 | + DPRINTF(1, (stderr, "os_sigcontext_sse2 mxcsr = #x%08lx\n", mxcsr));
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| 683 | + |
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| 684 | + return mxcsr;
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| 685 | +}
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| 686 | + |
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| 687 | +void
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| 688 | +os_set_sigcontext_sse2_modes(ucontext_t *scp, unsigned int modes)
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| 689 | +{
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| 690 | + fpregset_t *fpr;
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| 691 | + fpr = &scp->uc_mcontext.fpregs;
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| 692 | + |
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| 693 | + fpr->fp_reg_set.fpchip_state.mxcsr = modes;
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| 694 | + |
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| 695 | + DPRINTF(1, (stderr, "os_set_sigcontext_sse2 mxcsr = #x%08x\n", modes));
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| 696 | +}
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| 697 | +#endif
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| 698 | + |
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| 640 | 699 | unsigned int
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| 641 | 700 | os_set_sigcontext_fpu_modes(ucontext_t *scp, uint32_t modes)
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| 642 | 701 | {
|