Raymond Toy pushed to branch issue-355-solaris-x86-fp-trap-handler at cmucl / cmucl
Commits:
-
4f48c6cb
by Raymond Toy at 2024-08-29T07:36:36-07:00
2 changed files:
Changes:
| ... | ... | @@ -481,6 +481,7 @@ |
| 481 | 481 | (type system-area-pointer scp))
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| 482 | 482 | (let* ((modes (sigcontext-floating-point-modes
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| 483 | 483 | (alien:sap-alien scp (* unix:sigcontext)))))
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| 484 | + (format t "Current modes: ~32,'0b~%" modes)
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| 484 | 485 | (multiple-value-bind (fop operands)
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| 485 | 486 | (let ((sym (find-symbol "GET-FP-OPERANDS" "VM")))
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| 486 | 487 | (if (fboundp sym)
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| ... | ... | @@ -503,6 +504,7 @@ |
| 503 | 504 | ;;
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| 504 | 505 | ;; Clear out the status for any enabled traps. If we don't
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| 505 | 506 | ;; then when we return, the exception gets signaled again.
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| 507 | + #+nil
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| 506 | 508 | (let* ((trap-bit (third (assoc code +fpe-code-info-alist+)))
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| 507 | 509 | (current-x87-modes (vm::x87-floating-point-modes))
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| 508 | 510 | (current-sse2-modes (vm::sse2-floating-point-modes))
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| ... | ... | @@ -525,7 +527,16 @@ |
| 525 | 527 | (setf (vm::x87-floating-point-modes) new-x87-modes))
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| 526 | 528 | |
| 527 | 529 | (format t "new x87 modes: ~32,'0b~%" (vm::x87-floating-point-modes))
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| 528 | - (format t "new sse2 modes: ~32,'0b~%" (vm::sse2-floating-point-modes)))))))
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| 530 | + (format t "new sse2 modes: ~32,'0b~%" (vm::sse2-floating-point-modes)))
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| 531 | + (let* ((trap-bit (third (assoc code +fpe-code-info-alist+)))
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| 532 | + (new-modes
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| 533 | + (dpb (logandc2 (ldb float-exceptions-byte modes)
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| 534 | + trap-bit)
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| 535 | + float-exceptions-byte modes)))
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| 536 | + (format t "New modes: ~32,'0b~%" new-modes)
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| 537 | + (setf (sigcontext-floating-point-modes)
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| 538 | + (alien:sap-alien scp (* unix:sigcontext))
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| 539 | + new-modes))))))
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| 529 | 540 | |
| 530 | 541 | (macrolet
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| 531 | 542 | ((with-float-traps (name merge-traps docstring)
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| ... | ... | @@ -637,6 +637,45 @@ os_sigcontext_fpu_modes(ucontext_t *scp) |
| 637 | 637 | return modes;
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| 638 | 638 | }
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| 639 | 639 | |
| 640 | +unsigned int
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| 641 | +os_set_sigcontext_fpu_modes(ucontext_t *scp, uint32_t modes)
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| 642 | +{
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| 643 | + unsigned short cw, sw;
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| 644 | + fpregset_t *fpr;
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| 645 | + unsigned int state;
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| 646 | +
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| 647 | + fpr = &scp->uc_mcontext.fpregs;
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| 648 | + |
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| 649 | + cw = modes & 0x3f;
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| 650 | + sw = (modes >> 7) &0x3f;
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| 651 | + |
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| 652 | + DPRINTF(1, (stderr, "modes = 0x%08x\n", modes));
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| 653 | + DPRINTF(1, (stderr, "cw = 0x%04x\n", cw));
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| 654 | + DPRINTF(1, (stderr, "sw = 0x%04x\n", sw));
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| 655 | + |
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| 656 | + fpr->fp_reg_set.fpchip_state.state[0] = cw;
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| 657 | + fpr->fp_reg_set.fpchip_state.state[1] = sw;
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| 658 | +
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| 659 | +#ifdef FEATURE_SSE2
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| 660 | + /*
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| 661 | + * Add in the SSE2 part, if we're running the sse2 core.
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| 662 | + */
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| 663 | + if (fpu_mode == SSE2) {
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| 664 | + unsigned long mxcsr = modes & 0xffff;
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| 665 | + |
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| 666 | + DPRINTF(1, (stderr, "SSE2 modes = %08lx\n", mxcsr));
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| 667 | + fpr->fp_reg_set.fpchip_state.mxcsr = mxcsr;
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| 668 | + |
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| 669 | + modes |= mxcsr;
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| 670 | + }
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| 671 | +#endif
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| 672 | + |
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| 673 | + modes ^= (0x3f << 7);
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| 674 | + return modes;
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| 675 | +}
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| 676 | + |
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| 677 | + |
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| 678 | + |
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| 640 | 679 | boolean
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| 641 | 680 | os_support_sse2()
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| 642 | 681 | {
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