Raymond Toy pushed to branch arm64-dev-1 at cmucl / cmucl

Commits:

2 changed files:

Changes:

  • src/compiler/arm64/arith.lisp
    ... ... @@ -772,6 +772,14 @@
    772 772 
       (:affected)
    773 773 
       (:policy :fast-safe))
    774 774
    775 
    +;;; INTEGER-WITH-A-BITE-OUT -- the full signed S-bit range with the top BITE
    776 
    +;;; values removed from the upper end.  That is:
    777 
    +;;;   (integer -(2^(s-1))  (2^(s-1) - bite - 1))
    778 
    +;;;
    779 
    +;;; Useful for immediate constants where the maximum positive value must be
    780 
    +;;; avoided to prevent overflow in subsequent arithmetic.  Examples:
    781 
    +;;;   (integer-with-a-bite-out 14 4) => (integer -8192 8187)  ; 14-bit signed, top 4 missing
    782 
    +;;;   (integer-with-a-bite-out  8 1) => (integer -128   126)  ; 8-bit signed, top 1 missing
    775 783 
     (deftype integer-with-a-bite-out (s bite)
    776 784 
       (cond ((eq s '*) 'integer)
    777 785 
             ((and (integerp s) (> s 1))

  • src/compiler/arm64/parms.lisp
    1 
    -;;; -*- Package: SPARC -*-
    1 
    +;;; -*- Package: ARM64 -*-
    2 2 
     ;;;
    3 3 
     ;;; **********************************************************************
    4 4 
     ;;; This code was written as part of the CMU Common Lisp project at
    ... ... @@ -10,49 +10,53 @@
    10 10 
     ;;; **********************************************************************
    11 11 
     ;;;
    12 12 
     ;;;    This file contains some parameterizations of various VM
    13 
    -;;; attributes for ARM.  This file is separate from other stuff so
    14 
    -;;; that it can be compiled and loaded earlier.
    13 
    +;;; attributes for the ARM64 (AArch64) architecture.  This file is
    14 
    +;;; separate from other stuff so that it can be compiled and loaded
    15 
    +;;; earlier.
    15 16 
     ;;;
    16 
    -;;; Converted from SPARC to ARM.
    17 
    +;;; Written by Rob MacLachlan (original SPARC version).
    18 
    +;;; Converted to ARM64 by [ARM64 port contributors].
    19 
    +;;; Derived from the SPARC and PPC ports.
    17 20 
     ;;;
    18 21
    19 22 
     (in-package "ARM64")
    20 
    -;;(intl:textdomain "cmucl-sparc-vm")
    23 
    +(intl:textdomain "cmucl-arm64-vm")
    21 24 
     (use-package "C")
    22 25
    23 
    -
    26 
    +
    24 27 
     ;;;; Compiler constants.
    25 28
    26 29 
     (eval-when (compile eval load)
    27 30
    28 
    -(adjoin :linux (backend-features *target-backend*))
    29 31 
     (setf (backend-name *target-backend*) "ARM64")
    30 
    -(setf (backend-version *target-backend*)
    31 
    -      "ARM64/Linux")
    32 
    -
    32 
    +(setf (backend-version *target-backend*) "ARM64/AArch64")
    33 33 
     (setf (backend-fasl-file-type *target-backend*) "arm64f")
    34 34 
     (setf (backend-fasl-file-implementation *target-backend*)
    35 
    -      arm-fasl-file-implementation)
    35 
    +      arm64-fasl-file-implementation)
    36 36 
     (setf (backend-fasl-file-version *target-backend*) byte-fasl-file-version)
    37 37 
     (setf (backend-register-save-penalty *target-backend*) 3)
    38 
    -
    39 
    -;; Only supporting little-endian ARM for now.
    38 
    +;; AArch64 is a little-endian architecture by default (BE8 mode exists
    39 
    +;; but is uncommon and not targeted here).
    40 40 
     (setf (backend-byte-order *target-backend*) :little-endian)
    41 41 
     (setf (backend-page-size *target-backend*) 4096)
    42 42
    43 
    +;;; Foreign linkage space.  The start address must match arm64-validate.h
    44 
    +;;; and the entry size must agree with arm64-arch.c.  Each entry is a
    45 
    +;;; ADRP + ADD + BR sequence (3 instructions = 12 bytes), rounded up to
    46 
    +;;; 16 bytes for alignment.
    43 47 
     (setf (c::backend-foreign-linkage-space-start *target-backend*)
    44 
    -      #x0f000000
    48 
    +      #x0f800000
    45 49 
           (c::backend-foreign-linkage-entry-size *target-backend*)
    46 
    -      ;; FIXME: Update this when we figure out how to do
    47 
    -      ;; linkage-tables on ARM.
    48 50 
           16)
    51 
    +
    49 52 
     ); eval-when
    50 53
    51 54 
     (pushnew :new-assembler *features*)
    52 55
    53 
    -
    56 
    +
    54 57 
     ;;;; Machine Architecture parameters:
    55 58
    59 
    +(eval-when (:compile-toplevel :load-toplevel :execute)
    56 60 
     (export '(word-bits byte-bits char-bits word-shift word-bytes char-bytes
    57 61 
     	  fixnum-tag-bits fixnum-tag-mask positive-fixnum-bits
    58 62
    ... ... @@ -76,10 +80,13 @@
    76 80
    77 81 
     #+double-double
    78 82 
     (export '(double-double-float-digits))
    79 
    -
    83 
    +) ; eval-when
    84 
    +
    80 85
    81 86 
     (eval-when (compile load eval)
    82 87
    88 
    +;;; AArch64 is a 64-bit architecture: one Lisp descriptor occupies one
    89 
    +;;; 64-bit word.
    83 90 
     (defconstant word-bits 64
    84 91 
       "Number of bits per word where a word holds one lisp descriptor.")
    85 92
    ... ... @@ -92,21 +99,22 @@
    92 99 
     (defconstant char-bytes (truncate char-bits byte-bits)
    93 100 
       "Number of bytes needed to represent a character")
    94 101
    102 
    +;;; word-shift = log2(word-bytes) = log2(8) = 3
    95 103 
     (defconstant word-shift (1- (integer-length (/ word-bits byte-bits)))
    96 104 
       "Number of bits to shift between word addresses and byte addresses.")
    97 105
    98 106 
     (defconstant word-bytes (/ word-bits byte-bits)
    99 107 
       "Number of bytes in a word.")
    100 108
    109 
    +;;; AArch64 uses the same 3-bit lowtag scheme as SPARC/PPC.
    101 110 
     (defconstant lowtag-bits 3
    102 111 
       "Number of bits at the low end of a pointer used for type information.")
    103 112
    104 113 
     (defconstant lowtag-mask (1- (ash 1 lowtag-bits))
    105 114 
       "Mask to extract the low tag bits from a pointer.")
    106 
    -
    115 
    +
    107 116 
     (defconstant lowtag-limit (ash 1 lowtag-bits)
    108 
    -  "Exclusive upper bound on the value of the low tag bits from a
    109 
    -  pointer.")
    117 
    +  "Exclusive upper bound on the value of the low tag bits from a pointer.")
    110 118
    111 119 
     (defconstant fixnum-tag-bits (1- lowtag-bits)
    112 120 
       "Number of tag bits used for a fixnum")
    ... ... @@ -114,15 +122,20 @@
    114 122 
     (defconstant fixnum-tag-mask (1- (ash 1 fixnum-tag-bits))
    115 123 
       "Mask to get the fixnum tag")
    116 124
    117 
    -(defconstant positive-fixnum-bits (- word-bits fixnum-tag-bits 1)
    118 
    -  "Maximum number of bits in a positive fixnum")
    125 
    +(defconstant positive-fixnum-bits (- 32 fixnum-tag-bits 1)
    126 
    +  "Maximum number of bits in a positive fixnum.
    127 
    +  Although the machine word is 64 bits, fixnums are kept within a
    128 
    +  signed 32-bit range for compatibility with the rest of CMU CL.")
    119 129
    120 
    -;; FIXME: All of the IEEE-754 float parms should probably be split
    121 
    -;; into a separate file to be shared by all platforms using standard
    122 
    -;; IEEE-754 single and double precision floats.
    130 
    +;;; Float layout constants.  IEEE 754 applies uniformly across
    131 
    +;;; architectures; only the sign-bit position changes with word width.
    132 
    +;;; For AArch64 (64-bit word) we use bit 63 as the float sign bit, but
    133 
    +;;; for the 32-bit single-float representation the sign is still bit 31
    134 
    +;;; within the 32-bit encoding word.
    123 135 
     (defconstant float-sign-shift 31)
    124 136
    125 
    -(defconstant single-float-bytes 4)	; Bytes to hold a single-float
    137 
    +;;; Single-float (32-bit IEEE 754 binary32).  Identical to SPARC/PPC.
    138 
    +(defconstant single-float-bytes 4)
    126 139 
     (defconstant single-float-bias 126)
    127 140 
     (defconstant single-float-exponent-byte (byte 8 23))
    128 141 
     (defconstant single-float-significand-byte (byte 23 0))
    ... ... @@ -131,7 +144,8 @@
    131 144 
     (defconstant single-float-hidden-bit (ash 1 23))
    132 145 
     (defconstant single-float-trapping-nan-bit (ash 1 22))
    133 146
    134 
    -(defconstant double-float-bytes 8)	; Bytes to hold a double-float
    147 
    +;;; Double-float (64-bit IEEE 754 binary64).  Identical to SPARC/PPC.
    148 
    +(defconstant double-float-bytes 8)
    135 149 
     (defconstant double-float-bias 1022)
    136 150 
     (defconstant double-float-exponent-byte (byte 11 20))
    137 151 
     (defconstant double-float-significand-byte (byte 20 0))
    ... ... @@ -143,63 +157,101 @@
    143 157 
     (defconstant single-float-digits
    144 158 
       (+ (byte-size single-float-significand-byte) 1))
    145 159
    160 
    +;;; double-float-digits = 20 + 32 + 1 = 53 (IEEE 754 binary64).
    161 
    +;;; The literal 32 matches the SPARC formula; word-bits cannot be used
    162 
    +;;; here because on ARM64 word-bits is 64, which would give the wrong answer.
    146 163 
     (defconstant double-float-digits
    147 
    -  (+ (byte-size double-float-significand-byte) word-bits 1))
    164 
    +  (+ (byte-size double-float-significand-byte) 32 1))
    148 165
    149 166 
     #+double-double
    150 167 
     (defconstant double-double-float-digits
    151 168 
       (* 2 double-float-digits))
    152 169
    153 
    -;; ARM specific information
    154 
    -;; See B6.1.39: FPSCR, Floating-point Status and Control Regiser, PMSA
    155 
    -(defconstant float-denormal-trap-bit (ash 1 15))         ; IDE bit[15]
    156 
    -(defconstant float-inexact-trap-bit (ash 1 12))          ; IXE bit[12]
    157 
    -(defconstant float-underflow-trap-bit (ash 1 11))        ; UFE bit[11]
    158 
    -(defconstant float-overflow-trap-bit (ash 1 10))         ; OFE bit[10]
    159 
    -(defconstant float-divide-by-zero-trap-bit (ash 1 9))    ; DZE bit[9]
    160 
    -(defconstant float-invalid-trap-bit (ash 1 8))           ; IOE bit[8]
    161 
    -
    162 
    -(defconstant float-round-to-nearest 0)  ; #b00 Round to Nearest
    163 
    -(defconstant float-round-to-positive 1) ; #b01 Round towards Plus Infinity
    164 
    -(defconstant float-round-to-negative 2) ; #b10 Round towards Minus Infinity
    165 
    -(defconstant float-round-to-zero 3)     ; #b11 Round towards Zero
    166 
    -
    167 
    -(defconstant float-rounding-mode (byte 2 22))	  ; RMode bits[23:22]
    168 
    -
    169 
    -;; The trap enable bits are split with the IDE bit separate from the
    170 
    -;; rest of the enable bits.  We're ignoring the IDE bit for now until
    171 
    -;; float-traps support it.
    172 
    -(defconstant float-traps-byte (byte 5 8))	  ; Trap enable bits
    173 
    -;; There doesn't appear to be separate accrued (sticky) and current
    174 
    -;; exceptions.  We also ignore the IDC bit.
    175 
    -(defconstant float-sticky-bits (byte 5 0))	  ; Cumulative excection bits Bits[4:0]
    176 
    -(defconstant float-exceptions-byte (byte 5 0))	  ; Same as cumulative
    177 
    -
    178 
    -;; Flush-to-zero bit
    179 
    -(defconstant float-fast-bit (ash 1 24))
    170 
    +;;; AArch64 FPCR/FPSR trap and rounding-mode bits.
    171 
    +;;;
    172 
    +;;; FPCR layout (Floating-Point Control Register):
    173 
    +;;;   [26]   IDE  – Input Denormal exception trap enable
    174 
    +;;;   [25]   IXE  – Inexact trap enable
    175 
    +;;;   [24]   UFE  – Underflow trap enable
    176 
    +;;;   [23]   OFE  – Overflow trap enable
    177 
    +;;;   [22]   DZE  – Divide-by-Zero trap enable
    178 
    +;;;   [21]   IOE  – Invalid Operation trap enable
    179 
    +;;;   [23:22] RMode – Rounding mode
    180 
    +;;;
    181 
    +;;; FPSR layout (Floating-Point Status Register):
    182 
    +;;;   [4]    QC   – Cumulative saturation (SIMD)
    183 
    +;;;   [3]    IDC  – Input Denormal cumulative
    184 
    +;;;   [2:0]  –    (reserved)
    185 
    +;;;   Bits 0-4 of the low byte carry the IEEE exception sticky flags:
    186 
    +;;;   [4]    IXC  – Inexact
    187 
    +;;;   [3]    UFC  – Underflow
    188 
    +;;;   [2]    OFC  – Overflow
    189 
    +;;;   [1]    DZC  – Divide-by-Zero
    190 
    +;;;   [0]    IOC  – Invalid Operation
    191 
    +;;;
    192 
    +;;; The trap-enable bits in FPCR use the same bit positions as FPSR
    193 
    +;;; sticky flags, offset by 8.  We follow the SPARC convention and
    194 
    +;;; name the FPCR trap-enable fields here; the runtime uses them when
    195 
    +;;; installing/querying the floating-point environment.
    196 
    +
    197 
    +;;; Exception / trap-enable bit positions within their respective
    198 
    +;;; FPCR byte (bits 8..13) and FPSR byte (bits 0..4).
    199 
    +(defconstant float-inexact-trap-bit        (ash 1 4))  ; IXE / IXC
    200 
    +(defconstant float-underflow-trap-bit      (ash 1 3))  ; UFE / UFC
    201 
    +(defconstant float-overflow-trap-bit       (ash 1 2))  ; OFE / OFC
    202 
    +(defconstant float-divide-by-zero-trap-bit (ash 1 1))  ; DZE / DZC
    203 
    +(defconstant float-invalid-trap-bit        (ash 1 0))  ; IOE / IOC
    204 
    +(defconstant float-imprecise-trap-bit float-inexact-trap-bit)
    205 
    +
    206 
    +;;; Rounding mode encoding in FPCR bits [23:22].
    207 
    +(defconstant float-round-to-nearest  0)   ; RN  (ties to even)
    208 
    +(defconstant float-round-to-positive 1)   ; RP
    209 
    +(defconstant float-round-to-negative 2)   ; RM
    210 
    +(defconstant float-round-to-zero     3)   ; RZ
    211 
    +
    212 
    +;;; Byte descriptors for fields within the 32-bit FPCR value.
    213 
    +(defconstant float-rounding-mode   (byte 2 22))  ; RMode field
    214 
    +(defconstant float-traps-byte      (byte 6  8))  ; trap-enable bits 8..13
    215 
    +(defconstant float-exceptions-byte (byte 6  0))  ; FPSR sticky bits 0..5
    216 
    +(defconstant float-sticky-bits     (byte 6  0))  ; alias for exceptions
    217 
    +
    218 
    +;;; Flush-to-zero / fast mode bit in FPCR.
    219 
    +;;; When set, AArch64 flushes denormal inputs/outputs to zero
    220 
    +;;; (equivalent to the SPARC EFM bit).
    221 
    +(defconstant float-fast-bit (ash 1 24))    ; FZ bit in FPCR
    180 222
    181 223 
     ); eval-when
    182 224
    183 225 
     ;;; NUMBER-STACK-DISPLACEMENT
    184 226 
     ;;;
    185 227 
     ;;; The number of bytes reserved above the number stack pointer.
    186 
    -;;;
    187 
    -;;; FIXME: Use the right value!
    228 
    +;;; AArch64 does not have SPARC-style register windows, so no window-
    229 
    +;;; spill area is needed.  We reserve one word (8 bytes) as a
    230 
    +;;; red-zone / alignment pad to match common ABI expectations.
    188 231 
     (defconstant number-stack-displacement
    189 
    -  0)
    190 
    -
    232 
    +  (* 1 vm:word-bytes))
    233 
    +
    234 
    +
    191 235 
     ;;;; Description of the target address space.
    192 236
    237 
    +(eval-when (:compile-toplevel :load-toplevel :execute)
    193 238 
     (export '(target-read-only-space-start
    194 239 
     	  target-static-space-start
    195 240 
     	  target-dynamic-space-start
    196 241 
     	  target-foreign-linkage-space-start
    197 242 
     	  target-foreign-linkage-entry-size))
    243 
    +)
    198 244
    199 
    -;;; Where to put the different spaces.  Must match the C code!
    200 
    -;;;
    245 
    +;;; Where to put the different spaces.  Must match the C code (arm64-validate.h)!
    246 
    +;;;
    247 
    +;;; AArch64 virtual address space is 48 bits (256 TiB) with the low
    248 
    +;;; half available to user-space processes.  We place the Lisp spaces
    249 
    +;;; in the first gigabyte, mirroring the SPARC layout but noting that
    250 
    +;;; on AArch64 the upper 16 bits of a 64-bit address must match bit 47
    251 
    +;;; (tagged-address extension); user-space addresses are therefore in
    252 
    +;;; the range 0x0000_0000_0000_0000 – 0x0000_7FFF_FFFF_FFFF.
    201 253 
     (defconstant target-read-only-space-start #x10000000)
    202 
    -(defconstant target-static-space-start    #x30000000)
    254 
    +(defconstant target-static-space-start    #x28000000)
    203 255 
     (defconstant target-dynamic-space-start   #x40000000)
    204 256
    205 257 
     (defconstant target-foreign-linkage-space-start
    ... ... @@ -207,12 +259,12 @@
    207 259 
     (defconstant target-foreign-linkage-entry-size
    208 260 
       (c:backend-foreign-linkage-entry-size *target-backend*))
    209 261
    210 
    -
    262 
    +
    211 263 
     ;;;; Other random constants.
    212 264
    265 
    +(eval-when (:compile-toplevel :load-toplevel :execute)
    213 266 
     (export '(halt-trap pending-interrupt-trap error-trap cerror-trap
    214 267 
     	  breakpoint-trap function-end-breakpoint-trap
    215 
    -	  not-implemented-trap
    216 268 
     	  after-breakpoint-trap allocation-trap
    217 269 
     	  pseudo-atomic-trap
    218 270 
     	  object-not-list-trap object-not-instance-trap
    ... ... @@ -222,12 +274,15 @@
    222 274 
     #+heap-overflow-check
    223 275 
     (export '(dynamic-space-overflow-error-trap
    224 276 
     	  dynamic-space-overflow-warning-trap))
    277 
    +)
    225 278
    226 
    -;; These values are used as the immediate value in a UDF instruction.
    227 
    -;; Note that Linux on arm appears to use udf 16 as its trace/breakpoint
    228 
    -;; trap, so we shouldn't use this for Lisp.
    229 
    -(defenum (:suffix -trap :start 4)
    230 
    -  function-header			; This value must be a multiple of 4!
    279 
    +;;; Trap codes are encoded as the immediate operand of the UDF (Undefined
    280 
    +;;; instruction) used to signal synchronous traps to the runtime.  The
    281 
    +;;; encoding must match arm64-arch.c.
    282 
    +;;;
    283 
    +;;; We start at 8 (same as SPARC) to leave room for low values that may
    284 
    +;;; be used by the OS or debugger.
    285 
    +(defenum (:suffix -trap :start 8)
    231 286 
       halt
    232 287 
       pending-interrupt
    233 288 
       error
    ... ... @@ -239,14 +294,10 @@
    239 294 
       dynamic-space-overflow-warning
    240 295 
       #+heap-overflow-check
    241 296 
       dynamic-space-overflow-error
    242 
    -  not-implemented
    243 
    -  ;; This is the trap number to use when a pseudo-atomic section has
    244 
    -  ;; been interrupted.
    245 
    -  pseudo-atomic
    246 297 
       )
    247 298
    248 299 
     ;; Make sure this starts AFTER the last element of the above enum!
    249 
    -(defenum (:prefix object-not- :suffix -trap :start 20)
    300 
    +(defenum (:prefix object-not- :suffix -trap :start 16)
    250 301 
       list
    251 302 
       instance)
    252 303
    ... ... @@ -256,10 +307,12 @@
    256 307 
       function-prologue
    257 308 
       function-epilogue)
    258 309
    259 
    -
    310 
    +
    260 311 
     ;;;; Static symbols.
    261 312
    313 
    +(eval-when (:compile-toplevel :load-toplevel :execute)
    262 314 
     (export '(static-symbols static-functions))
    315 
    +)
    263 316
    264 317 
     ;;; These symbols are loaded into static space directly after NIL so
    265 318 
     ;;; that the system can compute their address by adding a constant
    ... ... @@ -303,8 +356,6 @@
    303 356 
         lisp::*free-interrupt-context-index*
    304 357 
         unix::*interrupts-enabled*
    305 358 
         unix::*interrupt-pending*
    306 
    -    lisp::*pseudo-atomic-atomic*
    307 
    -    lisp::*pseudo-atomic-interrupted*
    308 359
    309 360 
         ;; Foreign linkage stuff
    310 361 
         #+linkage-table
    ... ... @@ -314,22 +365,11 @@
    314 365 
         lisp::*cmucl-lib*
    315 366 
         lisp::*cmucl-core-path*
    316 367
    317 
    -    *binding-stack-pointer*
    318 
    -
    319 
    -    ;; The real C stack pointer
    320 
    -    *number-stack-pointer*
    321 
    -
    322 
    -    ;; The number frame pointer (aka NFP)
    323 
    -    *number-frame-pointer*
    324 
    -
    325 
    -    ;; Gc
    326 
    -    #-gencgc
    327 
    -    lisp::*allocation-pointer*
    328 
    -
    329 368 
         ;; Gencgc
    330 
    -    ;;
    331 369 
         #+gencgc
    332 370 
         *current-region-free-pointer*
    371 
    +    ;; current-region-end-addr is a 64-bit physical address; when read
    372 
    +    ;; back from Lisp it is a fixnum shifted left by fixnum-tag-bits.
    333 373 
         #+gencgc
    334 374 
         *current-region-end-addr*
    335 375
    ... ... @@ -342,9 +382,13 @@
    342 382 
         :key-and-value
    343 383 
         :key-or-value
    344 384
    385 
    +    ;; FP constants
    386 
    +    *fp-constant-0d0*
    387 
    +    *fp-constant-0f0*
    388 
    +
    345 389 
         lisp::*unidata-path*
    346 390 
         lisp::*lisp-implementation-version*
    347 
    -
    391 
    +
    348 392 
         ;; Some spare static symbols.  Useful for adding another static
    349 393 
         ;; symbol without having to do a cross-compile.  Just rename one
    350 394 
         ;; of these to the desired name.
    ... ... @@ -368,31 +412,51 @@
    368 412 
         ))
    369 413
    370 414
    371 
    -
    372 415 
     ;;;; Assembler parameters:
    373 416
    374 
    -;;; The number of bits per element in the assemblers code vector.
    375 
    -;;;
    417 
    +;;; The number of bits per element in the assembler's code vector.
    418 
    +;;; AArch64 instructions are always 32 bits wide (4 bytes), but the
    419 
    +;;; assembler code-vector element unit is still 8-bit bytes, matching
    420 
    +;;; every other CMU CL port.
    376 421 
     (defparameter *assembly-unit-length* 8)
    377 422
    378 
    -
    379 
    -(export '(pseudo-atomic-trap
    423 
    +
    424 
    +(eval-when (:compile-toplevel :load-toplevel :execute)
    425 
    +(export '(pseudo-atomic-trap allocation-trap
    380 426 
     	  pseudo-atomic-value pseudo-atomic-interrupted-value))
    427 
    +)
    428 
    +
    429 
    +;;;; Pseudo-atomic trap number.
    430 
    +;;;;
    431 
    +;;;; On AArch64 we encode synchronous traps with UDF (permanently
    432 
    +;;;; undefined instruction), whose 16-bit immediate is the trap code.
    433 
    +;;;; There is no software-trap instruction analogous to SPARC's TRAP,
    434 
    +;;;; so pseudo-atomic-trap is an alias for the pending-interrupt-trap
    435 
    +;;;; UDF code.  The value must match arm64-arch.c.
    436 
    +(defconstant pseudo-atomic-trap pending-interrupt-trap)
    437 
    +
    438 
    +;;;; Allocation trap number.
    439 
    +;;;;
    440 
    +;;;; This is the UDF immediate used when inline allocation overflows
    441 
    +;;;; the current region.  Must match arm64-arch.c.
    442 
    +(defconstant allocation-trap
    443 
    +  ;; allocation-trap is encoded as the UDF immediate in macros.lisp.
    444 
    +  ;; Re-export the value used there so C code and Lisp agree.
    445 
    +  ;;
    446 
    +  ;; The numeric value 31 (same as SPARC) is chosen to be distinct from
    447 
    +  ;; all values in the halt..after-breakpoint range (8..14) and the
    448 
    +  ;; object-not-*-trap range (16..17).
    449 
    +  31)
    450 
    +
    381 451 
     ;;;; Pseudo-atomic flag
    382 452 
     ;;;;
    383 
    -;;;; This value is added to *pseudo-atomic-atomic* to indicate a
    384 
    -;;;; pseudo-atomic section.
    453 
    +;;;; This value is ORed into ALLOC-TN (X14) to mark a pseudo-atomic
    454 
    +;;;; section, matching the SPARC and PPC convention of using the bit
    455 
    +;;;; just below the lowtag field.
    385 456 
     (defconstant pseudo-atomic-value (ash 1 (1- vm::lowtag-bits)))
    386 457
    387 458 
     ;;;; Pseudo-atomic-interrupted-mask
    388 459 
     ;;;;
    389 
    -;;;; This is a mask used to check if a pseudo-atomic section was
    390 
    -;;;; interrupted.  This is indicated by least-significant bit of
    391 
    -;;;; *pseudo-atomic-atomic* being 1.
    392 
    -;;;;
    393 
    -;;;; FIXME: This is based on the sparc port where the pseudo-atomic
    394 
    -;;;; stuff is implemented as bits on the alloc-tn.  We don't have an
    395 
    -;;;; alloc-tn on ARM.  So should we emulate that using
    396 
    -;;;; *pseudo-atomic-atomic* or use *pseudo-atomic-interrupted* as on
    397 
    -;;;; x86?
    460 
    +;;;; AArch64 (like SPARC) signals a pseudo-atomic interrupt via the
    461 
    +;;;; least-significant bit of ALLOC-TN.
    398 462 
     (defconstant pseudo-atomic-interrupted-value 1)

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