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at 2026-03-25T17:53:45-07:00

Change foreign-linkage-space-start type for arm64

Used to be (unsigned-byte 32), but for arm64, we want (unsigned-byte
64).  We could just use unsigned-byte, but for compatibility with
existing ports, use 32-bits except for arm64.

Compiling this causes a restartable error about BACKEND being defined
incompatibility.  Select the clobber-it restart.  (We should fix
this.)

@@ -1995,7 +1995,12 @@
                  (emit-format-move-wide segment ,sf ,opc #b100101 hw src
                                         (reg-tn-encoding rd)))
                 (fixup
 -                (note-fixup segment ,fixup-kind src)
 +                (let ((fixup-name (intern
 +                                   (symbolicate (symbol-name ,fixup-kind)
 +                                                (format nil "-~D" lsl))
 +                                   :keyword)))
 +                  ;; Fixup names are like :movz-0, :movz-16, :movz-32, :movz-48.
 +                  (note-fixup segment fixup-name src))
                  (emit-format-move-wide segment ,sf ,opc #b100101 hw 0
                                         (reg-tn-encoding rd)))))))))
    (def movn   0 1 :movn)   ; Move with NOT,  64-bit
@@ -3815,7 +3820,7 @@
             (inst movk temp (ldb (byte 16 16) delta) :lsl 16)
             (inst movk temp (ldb (byte 16 32) delta) :lsl 32)
             (inst movk temp (ldb (byte 16 48) delta) :lsl 48)
 -           (inst add dst src temp)))))))
 +           (inst add dst src temp))))))
  ;; code = fn - fn-ptr-type - header - label-offset + other-pointer-tag
  (define-instruction compute-code-from-fn (segment dst src label temp)
@@ -3883,8 +3888,12 @@
            (unless (zerop hw2) (inst movk reg hw2 :lsl 32))
            (unless (zerop hw3) (inst movk reg hw3 :lsl 48))))))
      (fixup
 +     ;; Pass the fixup to each instruction -- movz/movk note the fixup
 +     ;; internally with the appropriate LSL-encoded name.
       (inst movz reg value)
 -     (inst movk reg value :lsl 16))))
 +     (inst movk reg value :lsl 16)
 +     (inst movk reg value :lsl 32)
 +     (inst movk reg value :lsl 48))))
  (define-instruction-macro li (reg value)
    `(%li ,reg ,value))

@@ -45,7 +45,7 @@
  ;;; ADRP + ADD + BR sequence (3 instructions = 12 bytes), rounded up to
  ;;; 16 bytes for alignment.
  (setf (c::backend-foreign-linkage-space-start *target-backend*)
 -      #x0f800000
 +      #x600000000000
        (c::backend-foreign-linkage-entry-size *target-backend*)
 )
@@ -245,14 +245,13 @@
  ;;; Where to put the different spaces.  Must match the C code (arm64-validate.h)!
  ;;;
  ;;; AArch64 virtual address space is 48 bits (256 TiB) with the low
 -;;; half available to user-space processes.  We place the Lisp spaces
 -;;; in the first gigabyte, mirroring the SPARC layout but noting that
 -;;; on AArch64 the upper 16 bits of a 64-bit address must match bit 47
 +;;; half available to user-space processes. Note that on AArch64 the
 +;;; upper 16 bits of a 64-bit address must match bit 47
  ;;; (tagged-address extension); user-space addresses are therefore in
  ;;; the range 0x0000_0000_0000_0000 – 0x0000_7FFF_FFFF_FFFF.
 -(defconstant target-read-only-space-start #x10000000)
 -(defconstant target-static-space-start    #x28000000)
 -(defconstant target-dynamic-space-start   #x40000000)
 +(defconstant target-read-only-space-start #x610000000000)
 +(defconstant target-static-space-start    #x620000000000)
 +(defconstant target-dynamic-space-start   #x630000000000)
  (defconstant target-foreign-linkage-space-start
    (c:backend-foreign-linkage-space-start *target-backend*))

@@ -236,7 +236,8 @@
    ;; The foreign linkage space start and size
 -  (foreign-linkage-space-start 0 :type (unsigned-byte 32))
 +  (foreign-linkage-space-start 0 :type (unsigned-byte #-arm64 32
 +						      #+arm64 64))
    (foreign-linkage-entry-size 0 :type index))

Raymond Toy pushed to branch arm64-dev-1 at cmucl / cmucl

Commits:

3 changed files:

Changes: